The present invention generally relates to making sub-lithographic gate conductors using sidewall patterning techniques.
In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these high densities there has been and continues to be efforts toward scaling down the device dimensions on semiconductor wafers. In order to accomplish such high device packing density, smaller and smaller features sizes are required. This includes the width and spacing of conductive features and the surface geometry such as corners and edges of various features. Since numerous conductive features are typically present on a semiconductor wafer, the trend toward higher device densities is a notable concern.
The requirement of small features (and close spacing between adjacent features) requires high resolution photolithographic processes. In general, lithography refers to processes for pattern transfer between various media. It is a technique used for integrated circuit fabrication in which a silicon slice, the wafer, is coated uniformly with a radiation-sensitive film, the resist, and an exposing source (such as optical light, X-rays, or an electron beam) illuminates selected areas of the surface through an intervening master template, the photomask, for a particular pattern. The lithographic coating is generally a radiation-sensitized coating suitable for receiving a projected image of the subject pattern. Once the image is projected, it is indelibly formed in the coating. The projected image may be either a negative or a positive of the subject pattern. Exposure of the coating through the photomask causes a chemical transformation in the exposed areas of the coating thereby making the image area either more or less soluble (depending on the coating) in a particular solvent developer. The more soluble areas are removed in the developing process to leave the pattern image in the coating as less soluble polymer.
Projection lithography is a powerful and essential tool for microelectronics processing. However, lithography is not without limitations. Patterning features having dimensions of about 0.25 xcexcm or less with acceptable resolution is difficult at best, and impossible in some circumstances. Patterning conductive features including conductive lines and conductive silicon substances (such as amorphous silicon and polysilicon) with small dimensions is required in order to participate in the continuing trend toward higher device densities. Procedures that increase resolution, improved critical dimension control, and provide small conductive features are therefore desired.
The present invention provides methods of forming sub-lithographic gate conductors using sidewall patterning techniques. The sub-lithographic gate conductors may be formed into any type of electrical structure including a memory cell, such as a static random access memory (SRAM) cell. The width of the gate conductors formed in accordance with the present invention is dependent upon sidewall deposition techniques rather than photolithography techniques. In other words, the width of the gate conductors is determined mainly by the limitations of sidewall deposition techniques rather than the limitations of photolithography techniques. As a result, sub-lithographic gate conductors may be formed in a reliable manner. The present invention therefore effectively addresses the concerns raised by the trend towards the miniaturization of semiconductor devices.
In one embodiment, the present invention relates to a method of forming a circuit structure containing at least one sub-lithographic gate conductor involving the steps of providing a substrate comprising active regions and a preliminary gate conductor film over portions of the substrate and portions of the active regions; forming a sidewall template mask having at least one sidewall over a portion of the preliminary gate conductor film that is positioned over portions of the active regions; forming a sidewall film over the sidewall template mask, the sidewall film having a vertical portion adjacent the sidewall of the sidewall template mask and a horizontal portion in areas not adjacent the sidewall of the sidewall template mask; removing the horizontal portion of the sidewall film exposing a portion of the sidewall template mask and removing the sidewall template mask; providing a second mask over the portions of the preliminary gate conductor film that are not positioned over portions of the active regions; removing exposed portions of the preliminary gate conductor film thereby forming the circuit structure containing the sub-lithographic gate conductor and gate conductors; providing a trim mask over the active regions, portions of the sub-lithographic gate conductor and the gate conductors; and removing exposed portions of the sidewall film and portions of the preliminary gate conductor film under the sidewall film.
In another embodiment, the present invention relates to a method of forming a circuit structure containing at least one sub-lithographic gate conductor involving the steps of providing a substrate comprising active regions and a preliminary gate conductor film over portions of the substrate and portions of the active regions, the preliminary gate conductor film comprising one of polysilicon and amorphous silicon; forming a sidewall template mask having at least one sidewall over a portion of the preliminary gate conductor film that is positioned over portions of the active regions; forming a sidewall film over the sidewall template mask, the sidewall film having a vertical portion adjacent the sidewall of the sidewall template mask and a horizontal portion in areas not adjacent the sidewall of the sidewall template mask; removing the horizontal portion of the sidewall film exposing a portion of the sidewall template mask and removing the sidewall template mask; providing a second mask over portions of the preliminary gate conductor film that are not positioned over portions of the active regions; removing exposed portions of the preliminary gate conductor film thereby forming the circuit structure containing the sub-lithographic gate conductor having a width of about 200 nm or less and gate conductors; providing a trim mask over the active regions, portions of the sub-lithographic gate conductor and the gate conductors; and removing exposed portions of the sidewall film and portions of the preliminary gate conductor film under the sidewall film.
In yet another embodiment, the present invention relates to a method of forming a circuit structure containing at least one sub-lithographic gate conductor involving the steps of providing a substrate comprising active regions and a preliminary gate conductor film over portions of the substrate and portions of the active regions, the preliminary gate conductor film comprising one of polysilicon and amorphous silicon; etching a portion of the preliminary gate conductor film that is positioned over portions of the active regions forming a sidewall in the preliminary gate conductor film over portions of the active regions; forming a sidewall film over the preliminary gate conductor film, the sidewall film having a vertical portion adjacent the sidewall of the preliminary gate conductor film and a horizontal portion in areas not adjacent the sidewall of the preliminary gate conductor film; removing the horizontal portion of the sidewall film exposing portions of the preliminary gate conductor film; providing a mask over portions of the preliminary gate conductor film that are not over portions of the active regions; removing exposed portions of the preliminary gate conductor film forming the circuit structure containing the sub-lithographic gate conductor having a width of about 200 nm or less and gate conductors; providing a trim mask over the active regions, portions of the sub-lithographic gate conductor and the gate conductors; and removing exposed portions of the sidewall film and portions of the preliminary gate conductor film under the sidewall film.
In still yet another embodiment, the present invention relates to a method of forming a memory cell comprising a sub-lithographic gate conductor involving the steps of providing a substrate comprising active regions and a preliminary gate conductor film over portions of the substrate and portions of the active regions, the preliminary gate conductor film comprising polysilicon; forming a sidewall template mask over a portion of the preliminary gate conductor film, the sidewall template mask having at least one sidewall on a portion of the preliminary gate conductor film that is positioned over portions of the active regions; forming a sidewall film over the sidewall template mask, the sidewall film having a vertical portion adjacent the sidewall of the sidewall template mask and a horizontal portion in areas not adjacent the sidewall of the sidewall template mask; removing the horizontal portion of the sidewall film exposing a portion of the sidewall template mask using anisotropic etching; removing the exposed portions of the sidewall template mask exposing portions of the preliminary gate conductor film using anisotropic etching; providing a second mask over the substrate and portions of the preliminary gate conductor film that are not over portions of the active regions; removing exposed portions of the preliminary gate conductor film thereby forming a memory cell comprising the sub-lithographic gate conductor having a transistor channel length of about 200 nm or less and gate conductors having a width larger than the transistor channel length of the sub-lithographic gate conductor; providing a trim mask over the active regions, portions of the sub-lithographic gate conductor and the gate conductors; and removing the vertical portion of the sidewall film and portions of the preliminary gate conductor film under the sidewall film.